Welcome to Sentinel’s documentation!
Sentinel is a microcoded RISC-V CPU
(RV32I_Zicsr) written in Amaranth, implementing
the Machine Mode privileged spec. On FPGAs, it is designed to fit into:
~1000 4-input LUTs.
~400 FFs or less.
≥ 3 256 x 16 bit block RAMs for at least the microcode store (256 x ≥ 48 bit).
As is normal for microcoded designs, instructions take multiple clock cycles. The core’s size and speed makes it well suited for control tasks and system initialization, where a programmable state machine or custom size-tailored core would otherwise be used. In essence, the core “stands watch” over a more complex design, which is how I came up with the name (in addition to liking the word “Sentinel” from other sources from my childhood).
Sentinel will eventually be available on PyPI under the
package name sentinel-cpu. In the interim, use the
development repo instead.
The nice logo was contributed by the lovely Tokino Kei :D.